This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-M), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.

Qiyuan Liu is a Senior Engineer at Qualcomm.

Alexander Edward is a Senior Engineer at Intel.

Carlos Briseno-Vidrios is a Senior Engineer at Silicon Labs.

Jose Silva-Martinez got his PhD degree from the Katholieke Universiteit Leuven, Belgium in 1992. He currently holds the rank of Texas Instruments Professor in Analog Engineering at the Department of ECE, Texas A&M University. Dr. Silva-Martinez is an IEEE-Fellow and member of the 2013-2014 CASS Distinguish Lecture Program. His record of publications show over 100 journals and 160 conferences, 2 books and 12 book chapters and 1 patent. He is co-author of the papers that received the 2011 Best Student Paper Award, IEEE MWCAS, the 2003 Best Student Paper Award, IEEE RF-IC, and recipient of the 1990 Best Paper Award, European Solid-State Circuits Conference (ESSCIRC). He got the 2005 Outstanding Professor Award by the ECE Department, Texas A&M University, 2005; co-Advised in Testing techniques the student who was Winner ofthe 2005 Best Doctoral Thesis Award, presented by the IEEE Test Technology Technical Council (TTTC), IEEE Computer Society.

Introduction.- Analog-To-Digital and Digital-To-Analog Converters.- Delta-Sigma Modulators.- Design Considerations Of Mash CT-M.- A 43 mW MASH 2-2 CT Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS.- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.- A 4-Bit Continuous-Time Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer.- Conclusion.